1. Field of the Invention
This invention relates to a large scale integrated circuit (LSI), and more particularly to an LSI with a built-in clock generator-controller for an operation with low power dissipation.
2. Description of the Related Art
A conventional LSI of the type mentioned will be described with reference to the drawings.
FIG. 4 show in block diagram a construction of a clock controller for such a conventional microprocessor which operates with low power dissipation as disclosed in Japanese Patent Publication Application No. Heisei 4-12842. Referring to FIG. 4, the clock controller shown includes a phase locked loop circuit PLL formed from a phase detector 406, a low-pass filter 407, a voltage controlled oscillator 409 and a modulo divider 405, and a timing selector 411.
In the clock controller shown in FIG. 4, an oscillation output of an external quartz oscillator (not shown) is applied to the phase detector 406 by way of an external oscillation signal input terminal 401 and also to the timing selector 411 for achieving a low power dissipation operation. An output terminal of the phase detector 406 is connected to the low-pass filter 407 which passes only signals of a low frequency band, and an analog output terminal of the low-pass filter 407 is connected to the voltage controlled oscillator 409.
An on/off control signal 404 is inputted to a second input terminal 408 of the low-pass filter 407 and a second input terminal 410 of the voltage controlled oscillator 409. An output of the voltage controlled oscillator 409 is supplied to input terminals of the modulo divider 405 and the timing selector 411. An output of the modulo divider 405 is inputted to the other input terminal of the phase detector 406. A modulo control signal 402 is inputted to the modulo divider 405 and determines a dividing ratio. Further, a clock selector control signal 403 is inputted to the timing selector 411.
The phase locked loop circuit PLL functions based on an operation principle of a frequency phase locked loop and synchronizes the phase and the frequency of the output signal of the voltage controlled oscillator 409 with the phase and the frequency of an input signal thereto. More particularly, the phase locked loop circuit PLL synchronizes the phase and the frequency of the output signal of the voltage controlled oscillator 409 with the phase and the frequency of an external oscillation signal applied to the external oscillation signal input terminal 401. The output signal frequency fsyn of the voltage controlled oscillator is related to the external oscillation signal frequency fref in accordance with the following equation: EQU fsyn=M.times.fref
where M is a dividing coefficient of the modulo divider 405.
More particularly, the phase detector 406 compares the phase of the external oscillation signal (frequency: fref) with the phase of the output signal (frequency: fsyn/M) of the modulo divider 405 and produces an output signal which increases in proportion to a difference between the phases of the two signals. The output signal is applied to the input terminal of the low-pass filter 407. The low-pass filter 407 shapes the output signal of the phase detector 406, and an output signal of the low-pass filter 407 is applied to the frequency control input terminal of the voltage controlled oscillator 409. The voltage controlled oscillator 409 generates a signal having a frequency directly related to the value of a voltage VIN applied to the frequency control input terminal as given by the following equation: EQU fsyn=K.times.VIN
where K is a constant which depends upon a particular circuit parameter.
The output signal of the voltage controlled oscillator 409 is supplied to the modulo divider 405 which divides the frequency of an input signal thereto by the dividing coefficient M. The dividing coefficient M is determined by the modulo control signal 402. The output signal of the voltage controlled oscillator 409 is supplied also to the timing selector 411 which divides the frequency of the input signal thereto by another dividing coefficient N. The timing selector 411 divides the output signal of the voltage controlled oscillator 409 in accordance with the dividing ratio N designated by the clock selector control signal 403 and generates a clock signal for the microprocessor. The relationship between the power dissipation Pslow of the microprocessor when it operates with a clock signal of a low frequency and the power dissipation Pnormal of the microprocessor when it operates with a clock signal which has not been divided is given by the following equation: EQU Pnormal=N.times.Pslow
where N is a dividing ratio of the timing selector 411.
FIG. 5 shows in block diagram a construction of such a conventional clock outputting circuit as disclosed in Japanese Patent Laid-Open Application No. Heisei 4-25913.
Referring to FIG. 5, the clock outputting circuit shown has a buffer circuit 502 having an input terminal to which a clock input terminal 501 is connected and an output terminal connected to an external clock output terminal 503, and another buffer circuit 504 having an input terminal connected to the output of the buffer circuit 502 and an output terminal connected to an internal clock output terminal 505. The buffer circuits 502 and 504 are each formed from an IC and are mounted on a common circuit board.
In the circuit shown in FIG. 5, when the load capacity to the external clock output terminal 503 varies so that the delay time of the clock signal outputted from the external clock output terminal 503 with respect to the input signal to the clock input terminal 501 is varied, also the delay time of the clock signal outputted from the internal clock output terminal 505 is varied by an equal amount. Accordingly, the time difference between the clock signal outputted from the external clock output terminal 503 and the clock signal outputted from the internal clock output terminal 505 is always kept fixed. In short, the time difference (skew) can be suppressed substantially to zero.
In a system to which an LSI is applied, the entire system formed from the LSI operates with a clock signal supplied from a fixed frequency clock generator included in the system. While this configuration simplifies the circuit configuration of the system formed from the LSI, it limits, from the point of view of power dissipation, the performance demanded for the system.
When the calculation processing capacity varies with respect to time, the frequency of the system clock signal is set sufficiently high in order to supply a calculation processing capacity necessary to process a maximum processing amount to be executed by the system. In such a case, the system operates with the flock signal of the high frequency even when it performs processing for which the maximum processing capacity is not required. A system formed from a CMOS LSI dissipates higher power upon operation thereof with a high frequency. Accordingly, a system which is controlled by a fixed frequency clock signal dissipates a greater amount of power comparing with another system which is controlled by a variable frequency clock signal whose clock frequency varies high or low depending upon whether the processing amount is great or small. Such variable frequency clock signal contributes very much to reduction of the power dissipation of the entire system formed from an LSI.
Subsequently, it will be examined to adapt the way of thinking of such a conventional clock controller as shown in FIG. 4 to an entire system formed from an LSI.
The object of a conventional microprocessor which can operate with low power dissipation is to provide a variable frequency clock generator for a microprocessor whose frequency is varied in accordance with a request for calculation of the microprocessor, to provide a clock generator and a microprocessor which provide reduced power power dissipation of the combination of a variable clock generator and a microprocessor, and to provide a variable frequency clock generator which can be formed readily on a common chip with a microprocessor for which various integrated circuit techniques including a CMOS technique are used.
While the construction of a microprocessor described above contributes to reduction in power dissipation of a clock generator and a microprocessor provided on a common silicon material, it has some problem when it is applied to achieve reduction of power dissipation of an entire system formed from an LSI. In particular, when a microprocessor performs a low power dissipation operation, or in other words, a low frequency operation, also the entire system which operates in synchronism with the microprocessor must perform a low frequency operation with a system clock signal divided by an equal dividing ratio N. In order to supply the system clock signal for a low frequency operation, the fixed frequency clock generator of the conventional arrangement must be replaced with a variable frequency clock generator which is controlled by the microprocessor, or a low frequency clock signal generated in the microprocessor must be supplied to the outside.
When an external variable frequency clock generator is controlled by a microprocessor, it is difficult to control smooth switching between clock signals. While an external circuit is provided to interconnect the external clock generator and the microprocessor, depending upon variations of parameters of the external circuit and external conditions such as an operation temperature, such a short pulse (spike) as may cause a malfunction if the clock signal of the external clock generator is used as a clock signal for the microprocessor is produced upon switching between clock signals. The spike gives rise to a problem that it makes the microprocessor malfunction or, in the worst case, stop its operation. One of possible solutions to prevent such a malfunction of the microprocessor by a spike as described above is to use an on/off control signal for a phase locked loop circuit to stop operation of the phase locked loop circuit to stop supply of the clock signal to the microprocessor. This method, however, is disadvantageous in that switching between clock signals cannot be performed smoothly because the microprocessor stops its operation for a certain period of time.
Where a clock signal for a low frequency operation generated in a microprocessor is supplied as an external system clock signal, it is difficult to control to establish synchronism between the external system clock signal and an internal clock signal of the microprocessor. When the clock signal generated in the microprocessor is supplied to the outside, the number of external terminals, or in other words, the load, connected to an external system clock supplying output terminal varies depending upon the scale/configuration of the system, and this varies the delay time of the external system clock signal itself. Consequently, a difference in delay time between the internal clock signal and the external system clock signal, that is, a skew, is produced. The skew gives rise to a problem when communications synchronized with clocks are performed between the inside and the outside of the microprocessor.
Even if the manner of thinking of the conventional arrangement shown in FIG. 5 is applied to the problem of production of a skew which occurs with the conventional example described hereinabove with reference to FIG. 4, it still is difficult to supply an external system clock signal to the entire external system only from the buffer circuit 502 provided in the CMOS LSI. Consequently, an external clock driver is connected to the external clock output terminal 503, and an output of the external clock driver is used as an actual external system clock signal. Therefore, it is impossible to solve the problem that a skew is produced between the external system clock signal and the internal clock signal.